1. Field of the Invention.
The present invention relates to a method for reducing the likelihood that defects form during semiconductor device fabrication. More particularly, the present invention relates to a method for limiting defect formation by controlling the morphology of an implantation profile in a semiconductor substrate.
2. Description of the Related Art
There is a continuing trend toward increasing the storage density of integrated circuit memories to provide increased levels of data storage on a single chip. Higher density memories provide storage that is generally more compact and is often cheaper on a per bit basis than an equivalent amount of storage provided on plural chips. It has generally been possible to provide these higher levels of storage at equivalent or improved levels of performance as compared to earlier, less dense chips. Historically, the density of integrated circuit devices has been increased in part by decreasing the size of structures such as wiring lines and transistor gates and by decreasing the separation between the structures which make up the integrated circuit device. Reducing the size of circuit structures is generally referred to as decreasing the "design rules" used for the manufacture of the integrated circuit device.
In dynamic random access memories (DRAMs), information is typically stored by selectively charging or discharging each capacitor of an array of capacitors formed on the surface of a semiconductor substrate. Most often, a single bit of binary information is stored at each capacitor by associating a discharged capacitor state with a logical zero and a charged capacitor state with a logical one. The surface area of the electrodes of the memory capacitors determines the amount of charge that can be stored on each of the capacitors for a given operating voltage, for the electrode separation that can reliably be manufactured, and for the dielectric constant of the capacitor dielectric typically used between the electrodes of the charge storage capacitor. Read and write operations are performed in the memory by selectively coupling the charge storage capacitor to a bit line to either transfer charge to or from the charge storage capacitor. The selective coupling of the charge storage capacitor to the bit line is typically accomplished using a transfer field effect transistor (FET). The bit line contact is typically made to one of the source/drain electrodes of the transfer FET and the charge storage capacitor is typically formed in contact with the other of the source/drain electrodes of the transfer FET. Word line signals are supplied to the gate of the FET to connect one electrode of the charge storage capacitor through the transfer FET to the bit line contact facilitating the transfer of charge between the charge storage capacitor and the bit line.
FIG. 1 shows in schematic cross-section two memory cells of a DRAM at an intermediate stage of manufacture. The illustrated DRAM cells are formed on a P-type substrate 10 and include thick field oxide regions 12 to provide isolation from other, adjacent memory cells. A gate oxide layer 14 is formed by thermal oxidation on part of the active device region between the field oxidation regions and polysilicon gate electrodes 16 are formed on the gate oxide layer 14. The two gate electrodes 16 illustrated in FIG. 1 are part of two independent transfer FETs for the two illustrated memory cells. Polysilicon gate electrodes 16 are formed by depositing a layer of undoped polysilicon over the substrate, typically using low pressure chemical vapor deposition (LPCVD), and then implanting impurities into the polysilicon and activating the impurities to render the polysilicon layer conductive. The gate electrodes are then patterned using conventional photolithography techniques. A layer of silicon oxide 18 is provided over the polysilicon gate electrodes 16 to protect the gate electrodes in subsequent processing steps and, often, to serve as an etch stop for subsequent etching steps. Sidewall oxide spacer structures 20 are also provided adjacent the gate electrodes during the source/drain implantation process (discussed below). At the same time that the gate electrodes 16 are formed, wiring lines 22 which connect different gate electrodes are formed on field oxide regions 12. Because the wiring lines are generally formed in the same process used to form the gate electrodes 16, the wiring lines have a similar structure consisting of polysilicon lines 22 covered by oxide layers 24 with sidewall oxide spacer structures 26 formed alongside the wiring lines 22.
Doped source/drain regions 28, 30 and 32 are formed on either side of the polysilicon gate electrodes 16 to define the channel regions of the transfer FETs. The source/drain region 30 that is common to the transfer FETs will serve as the bit line contact for the two illustrated memory cells. Lightly doped drain (LDD) structures are often used in small design rule memory transistors of the type that are primarily used in modem memory and logic devices. LDD source/drain regions 28, 30 and 32 are typically formed in a two step process, beginning with a relatively low level dopant implantation made self-aligned to the polysilicon gate electrodes 16. Spacer oxide regions 20 are then formed on either side of the gate electrodes 16 by first depositing a layer of CVD oxide over the device and then anisotropically etching back the oxide layer to expose the substrate over the source/drain regions 28, 30 and 32. Etching back the CVD oxide layer produces the spacer oxide regions 20 on either side of the polysilicon gate electrodes 16 and on either side of the polysilicon wiring lines 22. After the spacer oxide regions 20 are provided on either side of the polysilicon gate electrodes 16, a second, heavier ion implantation is made into the source/drain regions 28, 30 and 32 self-aligned to the spacer oxide regions 20 to complete the source/drain regions.
After the formation of the transfer FETs of the DRAM cells, processing continues to form the charge storage capacitors and the bit line contacts by first depositing an insulating silicon oxide layer 34 over the FIG. 1 structure using chemical vapor deposition (CVD). The resulting structure is shown in FIG. 2. Openings 36 are then formed by conventional photolithography through the silicon oxide layer 34 to expose the source/drain regions 28, 32 of the substrate. Referring now to FIG. 3, a layer of undoped polysilicon 38 is next deposited by low pressure chemical vapor deposition (LPCVD) over the surface of the device and within the openings 36 in contact with source/drain regions 28, 32. Polysilicon layer 38 will form part of the lower electrode of the charge storage capacitor for the DRAM memory cells. The layer is doped by ion implantation and annealing and then the lower electrodes 38 are defined by photolithography. A capacitor dielectric layer 40, such as a two layer structure of silicon nitride and silicon oxide, is provided over the surfaces of the lower electrodes 38. Upper capacitor electrodes 42 are formed by depositing, doping and patterning a layer of polysilicon, producing the structure illustrated in FIG. 4.
Processing continues by blanket depositing a layer of interlayer dielectric material, such as a doped glass deposited by atmospheric pressure CVD from a TEOS source gas, over the FIG. 4 structure. A bit line contact 46 is opened through the dielectric layer 44 by conventional photolithography to expose the common source/drain contact 30. The bit line contact 50 is then formed, typically by providing an additional bit line contact ion implantation and then providing one or more layers of metal sputter or CVD deposited over the surface of the layer 44 and within the opening 46 as illustrated in FIG. 5. The bit line is then patterned and further processing is performed to complete the device.
Reducing the design rules used for forming the device illustrated in FIG. 5 places heightened demands on many of the structures illustrated in FIG. 5, along with the processing techniques used for forming the structures. The formation of source/drain regions becomes more critical because of the comparatively shallower and narrower source/drain regions that are incorporated in reduced dimension memory cells. There is a greater need to control implantation energies and the extent of diffusion of source/drain regions to achieve small device sizes. There is also a need to maintain highly conductive source/drain regions to maintain the high performance of these structures. An aspect of maintaining high conduction levels is preventing the formation of defect structures in the source/drain regions.
Several types of crystal lattice defect structures may be formed in the processes of implanting dopant ions into semiconductor substrates and annealing the substrates to activate the implanted dopants. The ion implant doses used in forming many semiconductor circuit components may render amorphous the crystalline silicon semiconductor substrate into which the dopant ions are implanted. The substrate must subsequently be annealed to activate the implantation and often to recrystallize the amorphous zone. Recrystallization of implanted silicon substrates occurs by solid-phase epitaxial (SPE) regrowth. SPE regrowth is a process in which the substrate is heated to a temperature below the melting point of the substrate material. Crystal growth occurs by solid state transport and proceeds over the boundary between the crystalline (implanted or unimplanted) portion of the substrate and the amorphous, implanted region of the substrate. The recrystallization occurs incrementally, with the direction of recrystallization of each incremental amorphous region determined by the orientation of the crystalline region on which the recrystallization takes place. Thus, the orientation of the crystalline substrate at the interface of the crystalline region and the amorphous region will determine the directions of SPE regrowth.
Due to the shape of the boundary of the amorphous region, it is possible for SPE regrowth to proceed along different crystalline planes. Various studies have indicated that SPE regrowth occurring along different crystalline planes can result in the formation of defects in the crystal. For example, the merging of growth fronts corresponding to two different crystal planes can result in the formation of extended defect structures in recrystallized silicon substrates. Other forms of residual defects may be introduced into the crystal lattice, both from implantation and from other processes. For example, the presence of gate layers and sidewall spacer layers on the substrate can introduce compressive stresses on the underlying material, particularly during subsequent thermal processing steps. The presence of such stresses may generate defects such as dislocations and can lead to dislocation multiplication.
Certain types of defects known as projected range defects (PRDs) and end of range defects (ERDs) may be formed in implanted and annealed regions of the substrate. PRDs and ERDs are secondary defects (dislocations or line defects), with PRDs located near the region of maximum implanted ion concentration and ERDs located near the amorphous-crystalline interface after implantation. These defects are believed to result from vertical SPE regrowth of amorphous silicon, that is, regrowth perpendicular to the silicon surface, and the defects may include dislocation loops buried within the implanted region. The location and density of PRDs and ERDs are related to the energy and dose of the implanting ions. Another type of defect related to recrystallization of a silicon made amorphous through ion implantation is the mask edge defect (MED). It is believed that MEDs are dislocations resulting from the merging of recrystallization fronts of vertical and lateral SPE regrowth. During the annealing and recrystallization process, the dislocations formed from the merging SPE regrowth fronts tend to agglomerate as additional epitaxial layers are formed, with the defects growing into a structure that has been described as being similar to a grain boundary. This extended defect structure can affect electron transport if it is positioned along a primary direction of current flow. Such defect structures may be formed near the lateral edges of the implantation zone at or near the substrate surface, often at the location where a recrystallizing substrate surface adjoins another structure on the surface of the substrate, and can lead to junction leakage problems.